VHDL errors and question

You have a couple of issues:

1. You cant use sll on std_logic_vectors because the "sll" function does not exist for that type. You have to use it on unsigned/signed type from the numeric_std library.

2. In VHDL, and integer is NOT an array of bits, so you cannot do bitwise operations on them. You have to convert the integer to an unsigned/signed or std_logic_vector type.

3. You cannot use sll/rol etc if you use those libraries. Use numeric_std instead.

4. I assune you're trying to produce synthesizable code? this is NOT going to work. Loops unroll when synthesized, and because your expression is not static (ie. a constant) it will complain. Loops are essentially N bits of hardware running in parrallel.

Overall, I suggest you go and read up on digital circuit design before trying to do stuff in VHDL. It is NOT a programming language.