VHDL errors and question

Humm, thank you for the replies :p!

I am trying to make a 8-bit signed adder (then I will make it a sub/adder), but I guess its working as a unsigned one, look at my code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity SubAdder is
    port(  worda: in std_logic_vector (7 downto 0);
            wordb: in std_logic_vector (7 downto 0);
            addsub: in std_logic;
            res: out std_logic_vector (7 downto 0);
            overflow: out std_logic
    );
    
end SubAdder;
architecture Func of SubAdder is
begin
process (worda,wordb,addsub)
begin
    res <= worda + wordb;
end process;
end Func;

But I guess its not working for negative numbers, should negative numbers be on the 2-complements form? Or the 8th bit '1' representing it as negative (+1)? I tried 81 + 01, it outputted 82 :p

Thank you again :)