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Altera_Forum's avatar
Altera_Forum
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16 years ago

VHDL errors and question

Hello! I am still learning vhdl and sorry if I made a question already answered on this forum. I am using Quartus II 8.1 web edition. I have 2 questions: 1- I am trying to use the operator...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The main problem you have is you're using std_logic_vectors for arithmatic. They are designed to just represent a collection of bits. They have no real meaning as unsigned or signed, and could be either.

If you scrap std_logic_signed package, and instead use ieee.numeric_std instead, you get access to types unsigned and signed.

So in your case, you could write your entity: 


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SubAdder is
    port(  worda: in signed(7 downto 0);
            wordb: in signed(7 downto 0);
            addsub: in std_logic;
            res: out signed(7 downto 0);
            overflow: out std_logic
    );
    
end SubAdder;
architecture Func of SubAdder is
begin
process (worda,wordb,addsub)
begin
  if addsub = '1' then
    res <= worda + wordb;
  else
    res <= worda - wordb;
  end if;
end process;
end Func;