VHDL 2008: Error (10500) in conditional assignment

According to my understanding VHDL-2008 should allow conditional assignment as a sequential statement, that is in clocked processes. However I get a syntax error 10500 in the below code fragment. Is that a bug in Quartus or an error on my side? In the latter case, what should the syntax be?

-- altera vhdl_input_version vhdl_2008
library ieee;
  use ieee.std_logic_1164.all;
  use work.all;
...
entity avs_ccm_gpio is
  generic(
    PORT_WIDTH : positive := 4;
    PORT_INIT    : std_logic_vector
  );
  port(
    areset          : in  std_logic;
    clk               : in  std_logic;
    ...
    GPIO_io         : inout std_logic_vector(PORT_WIDTH-1 downto 0)
  );
end entity;
architecture rtl of avs_ccm_gpio is
    signal CR           : std_logic_vector(11 downto 0);
    
    alias CR_LAT        : std_logic_vector(3 downto 0) is CR(3 downto 0);
    alias CR_DIR        : std_logic_vector(3 downto 0) is CR(7 downto 4);
    alias CR_DAT        : std_logic_vector(3 downto 0) is CR(11 downto 8);
    
    attribute altera_attribute : string;
    attribute altera_attribute of GPIO_io : signal is "-name FAST_OUTPUT_REGISTER ON; -name FAST_INPUT_REGISTER ON; -name FAST_OUTPUT_ENABLE_REGISTER ON";
begin
process(areset, clk)
  begin
    if(areset) then
     CR <= (others=>'0');
     
     for I in GPIO_io'range loop
       CR_DIR(I) <= '1' when PORT_INIT(I) /= 'Z' else '0'; -- Error (10500): VHDL syntax error near text "when";  expecting ";"
       CR_LAT(I) <= '1' when PORT_INIT(I) else '0'; -- Error (10500): VHDL syntax error near text "when";  expecting ";"
     end loop;
     avs_waitrequest <= '1';
   elsif(rising_edge(clk)) then
     ...
   end if;
end process;