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Altera_Forum
Honored Contributor
Honored ContributorVHDL 2008: Error (10500) in conditional assignment
According to my understanding VHDL-2008 should allow conditional assignment as a sequential statement, that is in clocked processes. However I get a syntax error 10500 in the below code fragment. Is ...
Altera_ForumHonored Contributor
Honored ContributorBtw checking that a port is = 'Z' is not possible inside the FPGA.
