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Honored ContributorVHDL 2008: Error (10500) in conditional assignment
According to my understanding VHDL-2008 should allow conditional assignment as a sequential statement, that is in clocked processes. However I get a syntax error 10500 in the below code fragment. Is ...
Altera_ForumHonored Contributor
Honored ContributorYes this is legal VHDL 2008, but unless you're using Quartus Prime Pro 16.1, you only get limited 2008 support :
http://quartushelp.altera.com/14.1/mergedprojects/hdl/vhdl/vhdl_list_2008_vhdl_support.htm
