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Honored Contributor
Honored ContributorVery long compilation time
Hi,
I am having a problem with extremely long compilation time. A simple VHDL code is taking 1 hour to compile. I am using Quartus 15.1 Standard Edition (trial version). I have seen that in the compilation process, it always gets stuck at the fitter process. At this point it states " The Fitter is using Advanced Physical Optimization" as shown in the attached screen shot . I have also seen that during this process, my computer's CPU usage goes to 100%. Kindly advise how to speed up the compilation specially the fitting process. Misha21 Replies
Altera_ForumSo finally I solved this problem by disabling the parallel compilation in Quartus II.
I went to Assignments-->settings --> Compilation process settings --> Maximum processors allowed = 1 Also, I disabled Modelsim by going to EDA tool settings--> Simulation --> None. My VHDL code was able to compile in just 4 minutes. Hopefully it will be useful for other people.- Altera_Forum
Thanks for sharing the finding. It is kind of interesting because by default, the QII will utilize all the available processors to speed up the compilation. Seems like when you constrain to only 1 processor, it is even faster.
- Altera_Forum--- Quote Start --- Hi, I am having a problem with extremely long compilation time. A simple VHDL code is taking 1 hour to compile. I am using Quartus 15.1 Standard Edition (trial version). I have seen that in the compilation process, it always gets stuck at the fitter process. At this point it states " The Fitter is using Advanced Physical Optimization" as shown in the attached screen shot . I have also seen that during this process, my computer's CPU usage goes to 100%. Kindly advise how to speed up the compilation specially the fitting process. Misha --- Quote End --- try different device. I have been through that
- Altera_Forum
What is this "simple" vhdl?
- Altera_Forum--- Quote Start --- What is this "simple" vhdl? --- Quote End --- Simple VHDL code means that my VHDL code is a very simple counter implementation. It is not a very long or complex code. Just a simple addition based on input clock. To fit this small code, it is taking 1-2 hrs. I cannot use a different device currently. Can you advise some other alternative?
- Altera_Forum
By the way, what is the device family that you are using?
- Altera_Forum
This does sound like an odd bug, and one that should be raised with altera to look at via mysupport
- Altera_Forum
hi, kind of surprise to heat this as now a days computer come with powerful systems, did you installed some resource consuming antivirus or real time threat scanner running at the background?
- Altera_Forum
oh ) nice Misha.kumar ...
The quartus contain many small files even i mark all as trusted software for antivirus. <- degraded perfomance with factor up to 2. then virual memory used at fitter stage is quite big. <- is it enough , so you don't enlarge disk swap. Accelarated launch and prioity changing on the fly with so called "Live optimizaton" software <- it creates troubles with quartus2 I wonder the time per stage in report file and actual real time -> for example 15 sec in report and 4 minutes in realtime. - Altera_Forum--- Quote Start --- oh ) nice Misha.kumar ... The quartus contain many small files even i mark all as trusted software for antivirus. <- degraded perfomance with factor up to 2. then virual memory used at fitter stage is quite big. <- is it enough , so you don't enlarge disk swap. Accelarated launch and prioity changing on the fly with so called "Live optimizaton" software <- it creates troubles with quartus2 I wonder the time per stage in report file and actual real time -> for example 15 sec in report and 4 minutes in realtime. --- Quote End --- excellent analysis !
