For project built in the Quartus, what files I need to commit to version control system? For HDL and sdc files are straightforward, how about files related IPs? Meanwhile, what is the best approach for another designer to rebuild the committed project in their local copy? Thanks in advance.

You need the .qpf and qsf files. What IPs are you talking about? any standard megafunctions (fifos, memories etc) you only need the wrapper HDL file, as this just calls the standard altera libraries. For any other IP, generally you would check in any HDL files generated, plus any TCL files it may have generated (which are usually just file lists to save you having to include all the HDL files manually in your project).

The best way to make sure you have everything: 1. check in what you think you need 2. do a clean checkout/update in a fresh directory 3. try and compile. 4. If you get any failures, go back to step 1. 5. Ask someone else to start at step 1.

--- Quote Start --- You need the .qpf and qsf files. What IPs are you talking about? any standard megafunctions (fifos, memories etc) you only need the wrapper HDL file, as this just calls the standard altera libraries. For any other IP, generally you would check in any HDL files generated, plus any TCL files it may have generated (which are usually just file lists to save you having to include all the HDL files manually in your project). --- Quote End --- Thanks for reply. So: 1. .qpf and qsf files are for project, correct? 2. So for IPs (no matter standard megafunctions or other IPs), the files I need to check are HDL files and tcl files? My questions are if I only check these HDLs and tcl files, after I rebuilt the project, includes all these files, how can I reconfigure these IPs if needed? 3. Is there a IP file that Quartus can regenerate the IP with same configuration based on this IP file? The reason I ask this since I used Xilinx FPGA for a while and come back to Altera FPGA for the current project. For IPs from Xilinx, there is a .xsi file that I can check in and Xilinx IDE can use this file to regenerate the IPs with same configuration as I did before. I wonder whether Altera has the similar mechanism. Thanks.

1. Yes. They define all the settings like pinouts etc. SDC files will have timing info. 2. What IPs are you talking about? IIRC, the megawizard (or whetever it is now) only outputs HDL for standard elements (PLLS, rams, fifos etc) that are just wrappers around the altera_mf library. So you only need these wrapper files. it should detect its a megawizard output when compiling (i think it dumps a load of data into the HDL comments). But you can avoid these IPs almost entirely by using i) Inference (so you can write behavioural, mostly portable VHDL code) http://www.altera.co.uk/literature/hb/qts/qts_qii51007.pdf ii) using the altera_mf library yourself (instantiate the megawizard IPs without using the megawizard). For example, the alsyncram megafunction can be found in quartus help. http://quartushelp.altera.com/13.0/mergedprojects/hdl/mega/mega_file_altsynch_ram.htm . The parameter list are the generics to the component. 3. As I said above, for most things altera generates HDL with metadata, rather than Xilinx's annoying default of generating cores. So its all HDL and text and human readible.

Thanks for detailed replies. That is great. Thanks a lot!

Version control for the Quartus project | Altera Community

17 Replies

Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
ive not used a lot of Qsys - but from memory the Qsys system is nothing to do with the quartus project. Qsys generates the files for quartus to compile. So after a fresh checkout, you need to re-generate the qsys system before compiling.
Or you could check in all the files Qsys generates (but this way gets very messy).
--- Quote End ---

It looks like that. No, I don;t want commit all files. I want to keep the commited designs compact.
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Hi, sorry but I didn't get following point: Would you please elaborate it in more details?

Regards,
Bhaumik
--- Quote End ---

I mean:

after I checkout my project, I open the project, in the project "IP components" tab, you won't see any qsys ip there. I have to open a qsys file then the project can auto load qsys IP into the project. Do you see the similar case?

Thanks.
Altera_Forum
Honored Contributor
11 years ago
Hello,

It seems due to .qip file generated by Qsys ( .qip will be available in synthesis folder once you generate QSYS design ) not added under version control. Could you try after adding all .qip files ( only .qip, not all Verilog and other files ) generated by QSYS in synthesis and its sub folders?

Thanks,
Bhaumik
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Hello,

It seems due to .qip file generated by Qsys ( .qip will be available in synthesis folder once you generate QSYS design ) not added under version control. Could you try after adding all .qip files ( only .qip, not all Verilog and other files ) generated by QSYS in synthesis and its sub folders?

Thanks,
Bhaumik
--- Quote End ---

The .QIP files files are just .tcl files that list the source code generated by QSYS, and any other assignments required. The should be generated from QSYS.
Altera_Forum
Honored Contributor
11 years ago
Hello all,

I did try to commit the .qip file generated by the qsys. Yes, now the qsys system is added into the project automatically. I think commit qsys .qip file is feasible since it is only a tcl file. No matter what, after you checkout the project, you need to regenerate the files from qsys.

Thanks.
Altera_Forum
Honored Contributor
8 years ago
Hello,

Tricky is right about .qip files. If we have .qsys file under version control, .qip is not required to be added. This is because when we regenerate .qsys, .qip file will be regenerated.

Regards,
Bhaumik
Altera_Forum
Honored Contributor
8 years ago
Minimum set for IP:

.v wrapper and megawizard .v

.qip, .sip

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Version control for the Quartus project

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