Forum Discussion
Altera_Forum
Honored Contributor
11 years agoHello,
It seems due to .qip file generated by Qsys ( .qip will be available in synthesis folder once you generate QSYS design ) not added under version control. Could you try after adding all .qip files ( only .qip, not all Verilog and other files ) generated by QSYS in synthesis and its sub folders? Thanks, Bhaumik