Altera_Forum
Honored Contributor
10 years agoVerliog - & and | operations backwards?
I am learning Verilog and at a stage in which I would like to see some results from my dev board.
I have started with a very simple program which takes two inputs and uses the "&" function to output the result to an LED. When running the program I noticed something was not right, I was getting the "or" function instead of an "and" function. After much dabbling I decided to try the "or" function instead, and to my surprise it was outputting the "and" function. I am not sure if I am doing something wrong or I have found a bug but I am most perplexed. The Quartus version I am running is 13.0s1 web edition and below is my code that I am running.module Test ( input in_1,
input in_2,
input clk,
output reg out_1
);
always @ (posedge clk)
begin
out_1 = (in_1 & in_2);
end
endmodule Any help is much appreciated!