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Altera_Forum
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11 years ago

Verliog - & and | operations backwards?

I am learning Verilog and at a stage in which I would like to see some results from my dev board. I have started with a very simple program which takes two inputs and uses the "&" function to outp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Found a solution to my own problem! I invert the inputs and then the output which gives a normal gate operation. 

out_1 <= ~(~in_1 & ~in_2);
Many thanks for your help!