Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Verliog - & and | operations backwards?

I am learning Verilog and at a stage in which I would like to see some results from my dev board. I have started with a very simple program which takes two inputs and uses the "&" function to outp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

One thing I noticed is that you are using posedge clk but you are using blocking assignment. Did you supply clock to your module?

You can try:

always @ (in_1, in_2)

begin

out_1 = (in_1 & in_2);

end

or if you have a clock supplied:

always @ (posedge clk)

begin

out_1 <= (in_1 & in_2);

end