Verilog Warning: No clocks defined in design

I'm using Cyclone IV DE2-115 board, I have tried connecting the CLOCK_50 input to the clocks pin according to this manual ftp://ftp.altera.com/up/pub/altera_material/13.0/boards/de2-115/de2_115_user_manual.pdf. I tried PIN_Y2 (CLOCK_50) as well as PIN_AE23 (SMA_CLKOUT) both this warning still persists. Any help would be greatly appreciated!

module uart(
	input wire CLOCK_50,						// map to onboard clock (50 MHz)
	input wire i_Rx_Channel,							// Rx channel, map to general purpose pin 
	input wire i_Tx_DV, 						// signals TX to read a byte to send
	input wire  i_Tx_Byte, 			// byte to be sent by Tx	
	output wire o_Tx_Channel,							// Tx channel, mapped to GPIO 1
	output wire o_Rx_Ready,
	output wire  received_Rx_byte);		// map to onboard LEDs for testing				
	parameter c_CLOCK_PERIOD_NS = 100;
	parameter c_CLKS_PER_BIT    = 434;
	parameter c_BIT_PERIOD      = 8600;
	uart_rx# ( 
		.CLKS_PER_BIT		(c_CLKS_PER_BIT)
	) receiver(
		.i_Clock				(CLOCK_50),
		.i_Rx_Serial		(i_Rx_Channel),
		.o_Rx_DV				(o_Rx_Ready),
		.o_Rx_Byte			(received_Rx_byte)
	);
	endmodule