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Altera_Forum
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7 years ago

Verilog Warning: No clocks defined in design

I'm using Cyclone IV DE2-115 board, I have tried connecting the CLOCK_50 input to the clocks pin according to this manual ftp://ftp.altera.com/up/pub/altera_material/13.0/boards/de2-115/de2_115_user_...
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Altera_Forum
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7 years ago

But it shouldnt affect whether my code works correct? Thanks!

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No clocks defined means you didn't create a .sdc file for timing analysis. You need to constrain the design.

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