Verilog vs Vhdl

While we were developing real pure low power ASICs on SUN workstations not based on FPGA designs, verilog HDL was the choice because all ASIC fabs requested verilog based verification sources.

well i guess it also depends what language you prefere or are used too.

for me VHDL is too much typo so i use verilog hdl.

Havent really used Verilog other than browsing round some code, but it seems to me that its structors much more like C than VHDL, so many people probably prefer it as they see it as easier to learn.

VHDL is strongly typed so you cant get away with alot. VHDL is great for typing exactly what you mean. It does mean VHDL is quite verbose though. Impressions I get online from people that do both, VHDL can do things quite neatly that verilog struggles with.

I was always under the impressions that its a bit of an ASIC vs FPGA thing : verilog was better for asics and VHDL better for FPGA. Also, I think VHDL can be better at abstracting things and behavioural models (though many people talk about systemverilog being as good if not better).

Just to Add:

Both Verilog and VHDL have been made into standards. VHDL in 1987, 1993, 2001 and 2008. Verilog in 1995, 1998 and 2001

Hi guys,

Thanks for all your opinions! Seems like you guys are in the industry, do they insist that you use Verilog in the industry?

Because I'm still in Uni and all they teach is VHDL, might be a problem when I get out of Uni.

Cheers,

Chris

well ... yes i am working for industrial applications.

but as BadOmen already said ... verilog is very much like c, so if you knew c you knew verilog and will be very fast being able to code in verilog.

but to say verilog is industrial.... i knew companies which only code in vhdl ...

things change from time to time. languages, prefered languages changes.

BTW ... who else has used AHDL in the past ? ;-)

Hi to everyone,

I have this problem when i do Starc Compilation but i don't know hot to do to solve it.

Internal Error: Sub-system: SUTIL, File: /quartus/synth/sutil/sutil_device.cpp, Line: 1242

is_legal_device()

Stack Trace:

0x9702: MEM_SEGMENT_INTERNAL::locked_allocate + 0x62 (ccl_mem)

0xa268: mem_realloc_wrapper + 0x188 (ccl_mem)

0x5580: mem_out_of_memory + 0x4f0 (ccl_mem)

0x82c5: MEM_SEGMENT_INTERNAL::allocate + 0x95 (ccl_mem)

End-trace

Quartus II Version 9.1 Build 304 01/25/2010 SJ Web Edition

Service Pack Installed: 1

Can someone help me please?

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Hi guys,

Thanks for all your opinions! Seems like you guys are in the industry, do they insist that you use Verilog in the industry?

Because I'm still in Uni and all they teach is VHDL, might be a problem when I get out of Uni.

Cheers,

Chris

--- Quote End ---

Dont worry about it. The language isnt the problem, its the understanding of the underlying hardware that matters. A monkey can learn a language, but engineers know how to use it properly. The language you use to describe it is much of a muchness. At the end of the date the gates and registers are the same.

and just to further your thoughts, heres a very good post from the VHDL newsgroup from someone who is very experienced with both languages:

--- Quote Start ---

> I think I have about had it with VHDL. I've been using the

> numeric_std library and eventually learned how to get around the

> issues created by strong typing although it can be very arcane at

> times. I have read about a few suggestions people are making to help

> with some aspects of the language, like a selection operator like

> Verilog has. But it just seems like I am always fighting some aspect

> of the VHDL language.

> I guess part of my frustration is that I have yet to see where strong

> typing has made a real difference in my work... at least an

> improvement.

I think Andy has it about right. If you think signed arithmetic

was a tad messy in VHDL, wait until you find how successfully you

can be screwed by Verilog. The really cool thing is that Verilog

is polite, and doesn't tell you when it's screwing you. At least

VHDL is up-front about it. How many times have you created a

design in VHDL that got through compilation, but was broken in

a surprising way that was directly related to a quirk of the

language? Betcha you can count the occurrences on one hand.

Verilog does that to you all the time; it has startlingly

weak compile-time checking, and only slightly stronger

elaboration-time checking.

How comfortable are you with most-significant bits being

silently lost when you copy a wide vector into a narrow

one? How about signed values being silently zero-filled

to the width of a wider target?

> My customer uses Verilog and has mentioned several times

> how he had tried using VHDL and found it too arcane to bother with.

> He works on a much more practical level than I often do and it seems

> to work well for him.

Is "practical" here a euphemism?

> One of my goals over the summer is to teach myself Verilog so that I

> can use it as well as I currently use VHDL. Then I can make a fully

> informed decision about which I will continue to use. I'd appreciate

> pointers on good references, web or printed.

Good luck. As I've pointed out on many occasions, the textbook

situation is much less satisfactory for Verilog than it is

for VHDL. Whatever you do, PLEASE get yourself a copy of

Sutherland's Verilog Gotchas book (much of it is available free

online). You may not understand all of it at first, but

you sure will want to revisit it later. It's just a pity

that it's incomplete and doesn't cover ALL the many ways

in which Verilog can silently mess you up.

To be serious for a moment: a training class from a

reputable independent provider will save you a ton

of money in the long run. Your time is valuable.

> Without starting a major argument, anyone care to share their feelings

> on the differences in the two languages?

Errrrm, I think I just did.

--- Quote End ---

Thanks guys for all your replies! You guys have been very helpful indeed and have really shed light on this topic for me. Really appreciate it.

Cheers,

Chris