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Altera_Forum
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16 years ago

Verilog vs Vhdl

Hi everyone, I was wondering why there were so few sources of VHDL around but many Verilogs and went on to search the differences between the two. However, all I get are either out of date...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi to everyone,

I have this problem when i do Starc Compilation but i don't know hot to do to solve it.

Internal Error: Sub-system: SUTIL, File: /quartus/synth/sutil/sutil_device.cpp, Line: 1242

is_legal_device()

Stack Trace:

0x9702: MEM_SEGMENT_INTERNAL::locked_allocate + 0x62 (ccl_mem)

0xa268: mem_realloc_wrapper + 0x188 (ccl_mem)

0x5580: mem_out_of_memory + 0x4f0 (ccl_mem)

0x82c5: MEM_SEGMENT_INTERNAL::allocate + 0x95 (ccl_mem)

End-trace

Quartus II Version 9.1 Build 304 01/25/2010 SJ Web Edition

Service Pack Installed: 1

Can someone help me please?