Verilog vs Vhdl

I used to be a die hard VHDL user but after giving Verilog a chance I can say that I hope to never see another line of VHDL ever again :) Like others have said VHDL is a more strict language which can be a good thing for catching mistakes. Verilog is a more relaxed and compact language since it closer resembles C which I like since I use HDL to make my life easier.... SystemVerilog seems to be language of the future so I'm not sure if VHDL will have another revision added later down the road in an attempt to get the same simulation features or if 2008 is the end of the line.