Verilog vs Vhdl

Havent really used Verilog other than browsing round some code, but it seems to me that its structors much more like C than VHDL, so many people probably prefer it as they see it as easier to learn.

VHDL is strongly typed so you cant get away with alot. VHDL is great for typing exactly what you mean. It does mean VHDL is quite verbose though. Impressions I get online from people that do both, VHDL can do things quite neatly that verilog struggles with.

I was always under the impressions that its a bit of an ASIC vs FPGA thing : verilog was better for asics and VHDL better for FPGA. Also, I think VHDL can be better at abstracting things and behavioural models (though many people talk about systemverilog being as good if not better).