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Hi guys,
Thanks for all your opinions! Seems like you guys are in the industry, do they insist that you use Verilog in the industry?
Because I'm still in Uni and all they teach is VHDL, might be a problem when I get out of Uni.
Cheers,
Chris
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Dont worry about it. The language isnt the problem, its the understanding of the underlying hardware that matters. A monkey can learn a language, but engineers know how to use it properly. The language you use to describe it is much of a muchness. At the end of the date the gates and registers are the same.
and just to further your thoughts, heres a very good post from the VHDL newsgroup from someone who is very experienced with both languages:
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> I think I have about had it with VHDL. I've been using the
> numeric_std library and eventually learned how to get around the
> issues created by strong typing although it can be very arcane at
> times. I have read about a few suggestions people are making to help
> with some aspects of the language, like a selection operator like
> Verilog has. But it just seems like I am always fighting some aspect
> of the VHDL language.
> I guess part of my frustration is that I have yet to see where strong
> typing has made a real difference in my work... at least an
> improvement.
I think Andy has it about right. If you think signed arithmetic
was a tad messy in VHDL, wait until you find how successfully you
can be screwed by Verilog. The really cool thing is that Verilog
is polite, and doesn't tell you when it's screwing you. At least
VHDL is up-front about it. How many times have you created a
design in VHDL that got through compilation, but was broken in
a surprising way that was directly related to a quirk of the
language? Betcha you can count the occurrences on one hand.
Verilog does that to you all the time; it has startlingly
weak compile-time checking, and only slightly stronger
elaboration-time checking.
How comfortable are you with most-significant bits being
silently lost when you copy a wide vector into a narrow
one? How about signed values being silently zero-filled
to the width of a wider target?
> My customer uses Verilog and has mentioned several times
> how he had tried using VHDL and found it too arcane to bother with.
> He works on a much more practical level than I often do and it seems
> to work well for him.
Is "practical" here a euphemism?
> One of my goals over the summer is to teach myself Verilog so that I
> can use it as well as I currently use VHDL. Then I can make a fully
> informed decision about which I will continue to use. I'd appreciate
> pointers on good references, web or printed.
Good luck. As I've pointed out on many occasions, the textbook
situation is much less satisfactory for Verilog than it is
for VHDL. Whatever you do, PLEASE get yourself a copy of
Sutherland's Verilog Gotchas book (much of it is available free
online). You may not understand all of it at first, but
you sure will want to revisit it later. It's just a pity
that it's incomplete and doesn't cover ALL the many ways
in which Verilog can silently mess you up.
To be serious for a moment: a training class from a
reputable independent provider will save you a ton
of money in the long run. Your time is valuable.
> Without starting a major argument, anyone care to share their feelings
> on the differences in the two languages?
Errrrm, I think I just did.
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