Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Verilog version works, VHDL doesn't

Hi. Apologies for the title choice but I can't think of anything else. I've decided to post this question in the VHDL section since that's where the problem seems to be for me. I have two source files, camera_test.vhd and camera_test.v . Both are the top level entity for the same QSYS based project. I wrote the VHDL one first but couldn't get it working so I decided to use Verilog on a whim to see if it would work, and it does. I've rechecked over and over and can't seem to find a difference between the two. I don't trust their reliability, but I even tried a Verilog to VHDL translator, and the resulting VHDL file doesn't work either. As far as I know both implementations should work, so that means I'm making a mistake but I can't find anything. I'd appreciate it if someone could help me on this.

Ammar

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    both are identical to me.

    Are you doing modelsim (it may not support mixed HDL but I expect warnings)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    No, I'm not using modelsim. The D5m camera is connected to a DE1 board and I'm checking if it works directly. There is a difference in the number of warnings produced when I compile both versions but that happens sometimes . This is just bizarre. I can upload the whole project as well if that can provide more information.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Check timing and you might have to do quick sim on same inputs

    and check your own observation at testing
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I see. I'll give it a shot but why would the output be different if the logic is the same? I don't know if this makes a difference, but the problem lies in the camera configuration since I can use the pixel buffer to display images on the vga. That only leaves the assignments for the AV configuration, the video in decoder, and the signal assignments. When I look at the LCD, the Verilog version gives a proper video output, but the VHDL version just gives noise, as if nothing is being retrieved from the camera. I've uploaded the project as well. Thank you for replying.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    The important thing is timing. If you have no timing specs, the timing between the VHDL and Verilog compiles could be completly different (each build with different sources will have a different start seed for the fit).

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Well that does make sense. However, I seem to have found the problem. It was the pixel clock reset for the video in decoder. Since I wasn't using that reset I completely forgot to assign it a value and left it as don't care. It has to be set as low so it doesn't interfere. Verilog doesn't have this problem. In fact the direction of a port isn't assigned in the internal modules in Verilog. I don't know much about Verilog so I don't really understand that part. Thank you for the input everyone.