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Altera_Forum's avatar
Altera_Forum
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11 years ago

Verilog version works, VHDL doesn't

Hi. Apologies for the title choice but I can't think of anything else. I've decided to post this question in the VHDL section since that's where the problem seems to be for me. I have two source file...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

No, I'm not using modelsim. The D5m camera is connected to a DE1 board and I'm checking if it works directly. There is a difference in the number of warnings produced when I compile both versions but that happens sometimes . This is just bizarre. I can upload the whole project as well if that can provide more information.