Verilog version works, VHDL doesn't

Well that does make sense. However, I seem to have found the problem. It was the pixel clock reset for the video in decoder. Since I wasn't using that reset I completely forgot to assign it a value and left it as don't care. It has to be set as low so it doesn't interfere. Verilog doesn't have this problem. In fact the direction of a port isn't assigned in the internal modules in Verilog. I don't know much about Verilog so I don't really understand that part. Thank you for the input everyone.