Verilog version works, VHDL doesn't

I see. I'll give it a shot but why would the output be different if the logic is the same? I don't know if this makes a difference, but the problem lies in the camera configuration since I can use the pixel buffer to display images on the vga. That only leaves the assignments for the AV configuration, the video in decoder, and the signal assignments. When I look at the LCD, the Verilog version gives a proper video output, but the VHDL version just gives noise, as if nothing is being retrieved from the camera. I've uploaded the project as well. Thank you for replying.