Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Verilog version works, VHDL doesn't

Hi. Apologies for the title choice but I can't think of anything else. I've decided to post this question in the VHDL section since that's where the problem seems to be for me. I have two source file...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

The important thing is timing. If you have no timing specs, the timing between the VHDL and Verilog compiles could be completly different (each build with different sources will have a different start seed for the fit).