Verilog Syntax Error

What is that "help" word doing there after begin ?

well you corrected the confusion but you should put endmodule at the end of module.

can you post the new code please

you should delete the first endmodule before begin, now that you moved down to the end of module

module de1sign (C, SW);
input  SW;
output  C;
assign C = SW;
assign C = SW;
endmodule
module codes (O, C, d, e, i) ; //possibility of using "i" if "1" is reserved.
input  C;
output d;
output e;
output i;
output O;
begin  
if ( C == 1'b0 && C == 1'b0);
O = d
if ( C == 1'b0 && C == 1'b1);
O = e
if ( C == 1'b1 && C == 1'b0);
O = i
end
endmodule
module hexcircuit (O, HEX0);
input O;
output  HEX0;
always @ (O);
begin
if ( O == d )
HEX0 = 7'b100_0010;
if ( O == e )
HEX0 = 7'b011_0000;
if ( O == i )
HEX0 = 7'b100_1111;
end
endmodule

is that "help" word part of code again?

First, for O outputs and others you should apply either priority logic of if ... else and not just if or use case statement if you don't want priority.