Verilog Syntax Error

--- Quote Start ---

you should delete the first endmodule before begin, now that you moved down to the end of module

--- Quote End ---

So this is the new code:

module de1sign (C, SW);
input  SW;
output  C;
assign C = SW;
assign C = SW;
endmodule
module codes (O, C, d, e, i) ; //possibility of using "i" if "1" is reserved.
input  C;
output d;
output e;
output i;
output O;
begin  
if ( C == 1'b0 && C == 1'b0);
O = d
if ( C == 1'b0 && C == 1'b1);
O = e
if ( C == 1'b1 && C == 1'b0);
O = i
end
endmodule
module hexcircuit (O, HEX0);
input O;
output  HEX0;
always @ (O);
begin
if ( O == d )
HEX0 = 7'b100_0010;
if ( O == e )
HEX0 = 7'b011_0000;
if ( O == i )
HEX0 = 7'b100_1111;
end
endmodule

i get:

Error (10170): Verilog HDL syntax error at de1sign.v(16) near text "begin"; expecting "endmodule"

Error (10170): Verilog HDL syntax error at de1sign.v(17) near text "=="; expecting ".", or an identifier

Error (10134): Verilog HDL Module Declaration error at de1sign.v(27): port "O" is declared more than once

Error (10170): Verilog HDL syntax error at de1sign.v(30) near text "begin"; expecting "endmodule"

Error (10112): Ignored design unit "codes" at de1sign.v(9) due to previous errors

Upon Compilation.

(post & code updated)