Altera_Forum
Honored Contributor
Honored ContributorVerilog Syntax Error
module de1sign (C, SW);
input SW;
output C;
assign C = SW;
assign C = SW;
endmodule
module codes (O, C, d, e, i) ; //possibility of using "i" if "1" is reserved.
input C;
output d;
output e;
out...
