Hi I've just learned that in Verilog you can use an `ifdef statement that makes Quartus ignore the following code (until the next`endif) you can define a macro in the qsf file (or through the GUI) to decide which parts of code to ignore. is there an equivalent in VHDL? the closest tool I'm aware of is the "if generate" statement but it is a weaker tool since: 1) you can use it only in the architecture body 2) the synthesizer first makes sure that the code inside the statement is compilable. this is a problem if you wish to omit other sections in the code. can anyone can enlighten me? I'm used to VHDL, but I this single feature will make me switch sides.:)

there is the option for: --synthesis translate_off any code here is ignored for synthesis, but will still run in a simulator. --synthesis translate_on While this is greate for simulation only processes and the like, it doesnt quite do what you want. The only way to do what you want is with generates.

Hi Tricky What I'm missing in the "--synthesis translate_off " statement is that it is not conditional. It's great if you have a bit of code that you wish to omit under some condition (synthesis verses simulation), but what happens if you want to replace a part of your design with something else? For example lets say I wish to instantiate a DFF instead of SRFF, In that case I will have to define the pins for the SRFF even when I'm using the generate statement for instantiating only the DFF. I can use the same pin names for both components, but for large designs it's confusing, and then you have width mismatch etc.

the only way you could do it is with generates. You could of course hide the generates under another level of heirarchy. Otherwise there is no way to do it, because there is no pre-compiler in VHDL.

--- Quote Start --- What I'm missing in the "--synthesis translate_off " statement is that it is not conditional. It's great if you have a bit of code that you wish to omit under some condition (synthesis verses simulation), but what happens if you want to replace a part of your design with something else? For example lets say I wish to instantiate a DFF instead of SRFF, In that case I will have to define the pins for the SRFF even when I'm using the generate statement for instantiating only the DFF. I can use the same pin names for both components, but for large designs it's confusing, and then you have width mismatch etc. --- Quote End --- There's a few methods that I've used; 1) For simulation vs synthesis -- altera translate_off Modelsim only ports or code goes here -- altera translate_on -- synthesis read_comments_as_HDL on -- Quartus-only code goes here (inside a comment block) -- synthesis read_comments_as_HDL off 2) For variations in hardware functionality I use generics and generate blocks, eg., to select between single-clock or dual-clock FIFOs in a bridge component. 3) For abstraction of components that differ between families, eg. RAM blocks (altsyncram vs lpm_ram_dq), use a component definition in the code, and then a VHDL configuration to map the component to the specific memory type. Cheers, Dave

Hi Dave All off these methods can be a little awkward when all you want is to change a couple of pins names in an entity with 30 - 40 pins. anyway I think I found my answer (http://www.vhdl.org/siwg/old-hm/0135.html)and it is a NO. now I have to decide if I rather use an external preprocessor or start to learn Verilog. I have to admit I was always convinced that anything you can do with VHDL you can do with Verilog and vica versa. I am a little bit surprised to learn that it isn't so.

Verilog `ifdef equivalent in VHDL | Altera Community

13 Replies

Altera_Forum
Honored Contributor
14 years ago
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If I remember right, the technique has been mentioned in several threads before. The most simple option is to keep all optional pins in the port definition of a common top entity file.

Use version dependent generate and if statements to access one or the other pin set. I'm using this method in several projects and don't see a problem with it.

I agree, that it would be convenient to have a Verilog or C alike preprocessor with VHDL. But I didn't experience a situation where the respective problem couldn't be handled with VHDL means somwhow.
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How do you place multiple ports onto the same pin in PinPlanner ... you can't I'd think?
Altera_Forum
Honored Contributor
14 years ago
I'm assuming, that each of the different FPGAs has it's own Quartus revision and respective pin assignments.
Altera_Forum
Honored Contributor
14 years ago
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Virtual pins actually consume an unconnected LE in gate level netlist, don't know why.
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I assume it has something to do with partitions. If you'll use your project as a partition in another project, that now virtual pin might become a constant driver.

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In my opinion, all these points aren't a sufficient reason to change the design top to Verilog.
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I tend to agree, though I've never worked with Verilog, I'm quite happy with the VHDL capabilities. that's why I'm writing a small preprocessor in tcl to add to the pre flow script.

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I'm assuming, that each of the different FPGAs has it's own Quartus revision and respective pin assignments.
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correct. I always assign pins in the qsf file, not in the VHDL code. I find it more readable, and reusable.

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Verilog `ifdef equivalent in VHDL

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