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If I remember right, the technique has been mentioned in several threads before. The most simple option is to keep all optional pins in the port definition of a common top entity file.
Use version dependent generate and if statements to access one or the other pin set. I'm using this method in several projects and don't see a problem with it.
I agree, that it would be convenient to have a Verilog or C alike preprocessor with VHDL. But I didn't experience a situation where the respective problem couldn't be handled with VHDL means somwhow.
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How do you place multiple ports onto the same pin in PinPlanner ... you can't I'd think?
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