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Virtual pins actually consume an unconnected LE in gate level netlist, don't know why.
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I assume it has something to do with partitions. If you'll use your project as a partition in another project, that now virtual pin might become a constant driver.
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In my opinion, all these points aren't a sufficient reason to change the design top to Verilog.
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I tend to agree, though I've never worked with Verilog, I'm quite happy with the VHDL capabilities. that's why I'm writing a small preprocessor in tcl to add to the pre flow script.
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I'm assuming, that each of the different FPGAs has it's own Quartus
revision and respective pin assignments.
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correct. I always assign pins in the qsf file, not in the VHDL code. I find it more readable, and reusable.
Honored Contributor
