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olcay
New Contributor
New ContributorVerilog code for ADC using DE1-SOC
Hello, My project is to convert an analog signal to digital, and I’m using the DE1-SoC ADC for this purpose. I’m trying to achieve this using the code from this video, but despite using the same cod...
FvM
Super Contributor
Super ContributorHi,
presently CS isn't operated in the code (only written low but never high). It should however go high and low again between 16 clock pulses. I also wonder what's the clk frequency and how it's generated?
My preferred SPI template uses a single edge sensitive process clocked at 2*SCLK, generating all output signals including SCLK synchronously.
Regards
Frank
