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New ContributorVerilog code for ADC using DE1-SOC
Hello,
My project is to convert an analog signal to digital, and I’m using the DE1-SoC ADC for this purpose. I’m trying to achieve this using the code from this video, but despite using the same code as in the video, my dout value always remains constant, and therefore my dataout value does not change. How can I solve this?
Example video Signal Tap Logic Analyzer
My ADC verilog code
`timescale 1ns / 10ps
module adcsignal(clk, sclk, din, dout, cs, count,dataout, clock_out,dataout2);
input clk;
output reg din;
output wire sclk;
input dout;
output reg cs;
output reg [11:0] dataout,dataout2;
reg [11:0] data_temp;
output reg clock_out;
reg ADD2,ADD1,ADD0;
output reg [3:0] count;
initial
begin
count = 4'd0;
cs = 1;
ADD2 = 0;
ADD1 = 1;
ADD0 = 0;
clock_out = 0;
dataout = 12'd0;
dataout2 = 12'd0;
data_temp = 12'd0;
end
always @(negedge clk)
begin
if (count == 0)
begin
cs <= 0;
end
end
assign sclk = cs?1:clk;
always @(posedge clk)
begin
count <= count + 4'd1;
end
always @(posedge clk)
begin
case (count)
1: begin
din <= ADD2;
end
2: begin
din <= ADD1;
end
3: begin
din <= ADD0;
ADD1 <= !ADD1;
end
endcase
end
always @(posedge clk)
begin
case(count)
3:
begin
if (ADD1 == 1)
dataout <= data_temp;
else
dataout2 <= data_temp;
end
4: data_temp[11] <= dout;
5: data_temp[10] <= dout;
6: data_temp[9] <= dout;
7: data_temp[8] <= dout;
8: data_temp[7] <= dout;
9: begin data_temp[6] <= dout;
clock_out <= 1;
end
10: begin data_temp[5] <= dout;
clock_out <= 0; end
11: data_temp[4] <= dout;
12: data_temp[3] <= dout;
13: data_temp[2] <= dout;
14: data_temp[1] <= dout;
15: data_temp[0] <= dout;
endcase
end
endmodule
