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Altera_Forum's avatar
Altera_Forum
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11 years ago

veilog code for demux unwanted latch at demux output problem

hey guys!! here is my code for 1:16 demux in verilog (quartus 2) 


module demux(sel, din , dout0 , dout1 ,dout2 , dout3 , dout4 , dout5 ,dout6 ,dout7 ,
                 dout8 ,dout9 , dout10 , dout1 , dout12 , dout13 , dout14 , dout15);
input  din;
input sel;
output dout0 ,dout1 ,dout2 ,dout3 ,dout4 ,dout5 ,dout6 ,dout7,
         dout8, dout9, dout10, dout11 ,dout12 ,dout13 , dout14 ,dout15;
         
reg    dout0 ,dout1,dout2 ,dout3 ,dout4 ,dout5 ,dout6 ,dout7,
         dout8 ,dout9 ,dout10 ,dout11 ,dout12 ,dout13 ,dout14 ,dout15 ;
         
always @(sel or din) begin
 case(sel)
     4'b0000: dout0 = din ; 
      4'b0001: dout1 = din ;
      4'b0010: dout2 = din ;
      4'b0011: dout3 = din ;
      4'b0100: dout4 = din ;
      4'b0101: dout5 = din ;
      4'b0110: dout6 = din ;
      4'b0111: dout7 = din ;
      4'b1000: dout8 = din ;
      4'b1001: dout9 = din ;
      4'b1010: dout10 = din ;
      4'b1011: dout11 = din ;
      4'b1100: dout12 = din ;
      4'b1101: dout13 = din;
      4'b1110: dout14 = din;
      4'b1111: dout15 = din;
      endcase
end
endmodule

after compilation i get this warning :

[h=3]verilog hdl always construct warning at <location>: inferring latch(es) for variable "<name>", which holds its previous value in one or more paths through the always construct[/h]

how can i write this code without getting this warning because i do not want any latches there...

any help is welcome.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    To prevent latches in combinatorial logic, you need to make sure that every bit of every variable has an assignment in every branch of the procedural code of your always block. You can do that by assigning a default value to every doutN bit before the case statement. 

    always @(sel or din) begin
 dout0 = 1'bx; dout1 = 1'bx; ...
 case(sel)
     4'b0000: dout0 = din ; 
      4'b0001: dout1 = din ;

    However a better way write this code is to index into a bit vector 

    module demux( // use Verilog-2001 syntax for your ports so you only have to declare these once, not up to 3 times
  input wire  din,
  input sel,
  output wire dout0 ,dout1 ,dout2 ,dout3 ,dout4 ,dout5 ,dout6 ,dout7,
         dout8, dout9, dout10, dout11 ,dout12 ,dout13 , dout14 ,dout15
);
reg  douts;
assign {dout0 ,dout1 ,dout2 ,dout3 ,dout4 ,dout5 ,dout6 ,dout7,
         dout8, dout9, dout10, dout11 ,dout12 ,dout13 , dout14 ,dout15} = douts;
always @(sel or din) begin
             douts = 16'bx;
             douts = din;
    end
endmodule
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    You are assign 16 different output latches.

    Each output holds it's previous value.

    If you don't want clock, make it an always @(posedge clk) block. Then the latches will be registers.

    Pete