Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

veilog code for demux unwanted latch at demux output problem

hey guys!! here is my code for 1:16 demux in verilog (quartus 2) module demux(sel, din , dout0 , dout1 ,dout2 , dout3 , dout4 , dout5 ,dout6 ,dout7 , dout8 ,dout9 , dout10 ,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

You are assign 16 different output latches.

Each output holds it's previous value.

If you don't want clock, make it an always @(posedge clk) block. Then the latches will be registers.

Pete