veilog code for demux unwanted latch at demux output problem

To prevent latches in combinatorial logic, you need to make sure that every bit of every variable has an assignment in every branch of the procedural code of your always block. You can do that by assigning a default value to every doutN bit before the case statement.

always @(sel or din) begin
 dout0 = 1'bx; dout1 = 1'bx; ...
 case(sel)
     4'b0000: dout0 = din ; 
      4'b0001: dout1 = din ;

module demux( // use Verilog-2001 syntax for your ports so you only have to declare these once, not up to 3 times
  input wire  din,
  input sel,
  output wire dout0 ,dout1 ,dout2 ,dout3 ,dout4 ,dout5 ,dout6 ,dout7,
         dout8, dout9, dout10, dout11 ,dout12 ,dout13 , dout14 ,dout15
);
reg  douts;
assign {dout0 ,dout1 ,dout2 ,dout3 ,dout4 ,dout5 ,dout6 ,dout7,
         dout8, dout9, dout10, dout11 ,dout12 ,dout13 , dout14 ,dout15} = douts;
always @(sel or din) begin
             douts = 16'bx;
             douts = din;
    end
endmodule