veilog code for demux unwanted latch at demux output problem

hey guys!! here is my code for 1:16 demux in verilog (quartus 2) module demux(sel, din , dout0 , dout1 ,dout2 , dout3 , dout4 , dout5 ,dout6 ,dout7 , dout8 ,dout9 , dout10 ,...