(vcom-1105) Name (indexed name) does not denote an entity name.
Hi,
Finally tracked down why I get this from modelsim-altera when using
Run Simulation Tool -> RTL Simulation
The generated PROJECT_run_msim_rtl_vhdl.do is not generated in correct order
file: cnf_regs_meas.vhd
ENTITY cnf_regs_meas IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT (...);
END cnf_regs_meas;
ARCHITECTURE cnf_regs_meas_architecture OF cnf_regs_meas IS
COMPONENT cnf_regs IS
GENERIC (...); PORT (...);
FOR REGS : cnf_regs USE ENTITY work.cnf_regs_generic(cnf_regs_generic_architecture);
BEGIN
END cnf_regs_meas_architecture;
file: cnf_regs_generic.vhd
ENTITY cnf_regs_generic IS
GENERIC (...)
PORT (...)
END cnf_regs_generic;
ARCHITECTURE cnf_regs_generic_architecture OF cnf_regs_generic IS
PROCESS ...
BEGIN
- - -
END PROCESS;
END cnf_regs_generic_architecture;
Problem is that PROJECT_run_msim_rtl_vhdl.do gets generated as, when cnf_regs_meas is compiled the required cnf_regs_generic does not exist in work.
- - -
vcom -2008 -work work {.../cnf_regs_meas.vhd}
vcom -2008 -work work {.../cnf_regs_generic.vhd}
- - -
Solution: swap compile order of these two files
Is there any other way?