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DavidB_EE's avatar
DavidB_EE
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1 year ago

Using the Pre-computed CRC on MAX10 FPGA to Determine .pof Version.

Hello,

I am wondering how and when the pre-computed CRC that gets loaded into the fpga CRC-correction block gets generated. I am able to get the CRC from both internal logic and by using the JAM player using CHANGE_EDREG, but am unable to find it when i inpect the .sof or .pof files that are generated by Quartus Prime. The link below indicates that the crc is precomputed by Quartus Prime, so it must be hiding somewhere in the programming files. Is this correct?

https://www.intel.com/content/www/us/en/docs/programmable/683865/current/configuration-error-detection.html

We are trying to find a way to check if the .pof that is loaded onto the fpga matches the .pof file that is stored on the host controller using the pre-computed CRC. If this is not possible, what is the best way to check if the .pof that is loaded into the flash of the fpga matches the .pof on the host controller without reflashing the fpga?

Thanks for looking into this for me.

-David

Compilation
Hdl

6 Replies

  • NurAiman_M_Intel's avatar
    NurAiman_M_Intel
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,


    Apologize for the delay in response.


    Per my understanding, you wanted to know if the .pof loaded into the FPGA is correct or not, right? For that, you may check the CRC. If there is no error at the CRC, meaning the .pof loaded is correct.


    Regards,

    Aiman


  • DavidB_EE's avatar
    DavidB_EE
    Icon for New Contributor rankNew Contributor
    1 year ago

    Aiman,

    That is not quite our goal.

    We want to be able to check to see if the .pof on the FPGA matches the .pof that we have on the host controller so that we can quickly check that the fpga has the latest image without flashing a new image to the FPGA flash. We were hoping to use the CRC to accomplish this and want to know if there is a way to extract the pre-computed CRC from the .pof file?

    We are using the Jam STAPL byte-code player to flash the fpga which is quite slow, so we want to update the fpga as little as possible.

    Thanks,

    David

  • NurAiman_M_Intel's avatar
    NurAiman_M_Intel
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,


    What is the nconfig, conf_done, nstatus signal? Does the conf_done goes high?


    Regards,

    Aiman


  • NurAiman_M_Intel's avatar
    NurAiman_M_Intel
    Icon for Super Contributor rankSuper Contributor
    1 year ago
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