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RobertLiang's avatar
RobertLiang
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Using simulation grammar in verilog file

Hello,

I use a few simulation grammars, such as $display $time in my Verilog design file.

I know these might be unsynthesisable codes, but I have seen many codes use simulation grammar in their design files, for example, to achieve parameter check such as:

initial begin
    if (WORD_SIZE * STRB_WIDTH != DATA_WIDTH) begin
        $error("Error: AXI data width not evenly divisble (instance %m)");
        $finish;
    end

    if (2**$clog2(WORD_WIDTH) != WORD_WIDTH) begin
        $error("Error: AXI word width must be even power of two (instance %m)");
        $finish;
    end
end

But I found when using Modelsim_altera and Quartus to perform simulation, the first step is to compile my design, but these unsynthesisable codes might lead to errors.

Is there any recommended method to do the same thing?

Thank you!

  • Nurina's avatar
    Nurina
    4 years ago

    Hi,


    OK so your version of Quartus supports Verilog-1995 and Verilog-2001. The system tasks you're using is that of SystemVerilog-2009. You should try replacing $error() with $display(). Make sure you set Verilog HDL Input to Verilog-2001 in the Compiler Settings.


    More information on Verilog-2001 system tasks can be found here in clause 17: https://ieeexplore.ieee.org/document/954909


    Regards,

    Nurina


5 Replies

  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    OK so your version of Quartus supports Verilog-1995 and Verilog-2001. The system tasks you're using is that of SystemVerilog-2009. You should try replacing $error() with $display(). Make sure you set Verilog HDL Input to Verilog-2001 in the Compiler Settings.


    More information on Verilog-2001 system tasks can be found here in clause 17: https://ieeexplore.ieee.org/document/954909


    Regards,

    Nurina


  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    You can use $error() and other system tasks from SystemVerilog-2009 & SystemVerilog-2012 but this is only supported in Quartus Prime Pro edition v17.0 and later. It will be ignored during synthesis. Why can't you have this in your testbench though? In the end you still want to do simulation.


    As far as I know, there isn't any synthesisable code with these functions. Perhaps you can assign a value to a pin for these kind of checks instead?


    Regards,

    Nurina


    • RobertLiang's avatar
      RobertLiang
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      Hi,

      I use Quartus standard edition v18.0, and using system task $time() in my Verilog design file will cause an error during synthesis.

      Do you mean that I should connect the internal signals with the top-level entity's pins, and then monitor these pins in my testbench? Is there any method to monitor them directly in the bottom-level entity?

      Thank you

  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

    Regards,
    Nurina

    PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.