Forum Discussion

RobertLiang's avatar
RobertLiang
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Using simulation grammar in verilog file

Hello, I use a few simulation grammars, such as $display $time in my Verilog design file. I know these might be unsynthesisable codes, but I have seen many codes use simulation grammar in their d...
  • Nurina's avatar
    Nurina
    4 years ago

    Hi,


    OK so your version of Quartus supports Verilog-1995 and Verilog-2001. The system tasks you're using is that of SystemVerilog-2009. You should try replacing $error() with $display(). Make sure you set Verilog HDL Input to Verilog-2001 in the Compiler Settings.


    More information on Verilog-2001 system tasks can be found here in clause 17: https://ieeexplore.ieee.org/document/954909


    Regards,

    Nurina


Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Regards,
Nurina

PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.