Forum Discussion
Occasional ContributorUsing simulation grammar in verilog file
Hi,
OK so your version of Quartus supports Verilog-1995 and Verilog-2001. The system tasks you're using is that of SystemVerilog-2009. You should try replacing $error() with $display(). Make sure you set Verilog HDL Input to Verilog-2001 in the Compiler Settings.
More information on Verilog-2001 system tasks can be found here in clause 17: https://ieeexplore.ieee.org/document/954909
Regards,
Nurina
Regular ContributorHi,
You can use $error() and other system tasks from SystemVerilog-2009 & SystemVerilog-2012 but this is only supported in Quartus Prime Pro edition v17.0 and later. It will be ignored during synthesis. Why can't you have this in your testbench though? In the end you still want to do simulation.
As far as I know, there isn't any synthesisable code with these functions. Perhaps you can assign a value to a pin for these kind of checks instead?
Regards,
Nurina
RobertLiangHi,
I use Quartus standard edition v18.0, and using system task $time() in my Verilog design file will cause an error during synthesis.
Do you mean that I should connect the internal signals with the top-level entity's pins, and then monitor these pins in my testbench? Is there any method to monitor them directly in the bottom-level entity?
Thank you
