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Occasional ContributorUsing simulation grammar in verilog file
Hi,
OK so your version of Quartus supports Verilog-1995 and Verilog-2001. The system tasks you're using is that of SystemVerilog-2009. You should try replacing $error() with $display(). Make sure you set Verilog HDL Input to Verilog-2001 in the Compiler Settings.
More information on Verilog-2001 system tasks can be found here in clause 17: https://ieeexplore.ieee.org/document/954909
Regards,
Nurina
Regular ContributorHi,
OK so your version of Quartus supports Verilog-1995 and Verilog-2001. The system tasks you're using is that of SystemVerilog-2009. You should try replacing $error() with $display(). Make sure you set Verilog HDL Input to Verilog-2001 in the Compiler Settings.
More information on Verilog-2001 system tasks can be found here in clause 17: https://ieeexplore.ieee.org/document/954909
Regards,
Nurina
Occasional ContributorThank you very much
