Honored ContributorHello, I would to know how accurate SignalTap is when capturing signals such as an 80-Mhz clock from a pll that is used to drive logic? When I view such a signal I see a non 50-percent duty cycle clock. My reference clock for SignalTap is my 80Mhz input clock. Could this be internal jitter on the clock from a pll?
Any ideas? Thanks, Joe
Honored ContributorIs there a reason why you need to see the clock in SignalTap? Remember, it's best if your sampling clock is twice the frequency of what you're monitoring. So with an 80 MHz sampling clock used to look at an 80 MHz clock, it may miss edges, which is what you are seeing.
Honored ContributorWell, I found an answer to my question. My co-worker said that SignalTap is not reliable to capture and show high rate clocks.
Honored ContributorThanks sstrell! I need to start thinking like an "engineer", how could I forget about sampling theory.
Honored ContributorIt's not entirely clear what you are saying. Are you saying you are trying to capture signals that are asynchronous to the 80 Mhz SignalTap clock. If so, then yes, there will be issues. But if you are capturing signals for registers driven by that clock, then it should not be a problem.
Honored ContributorHonored ContributorHi corestar,
Thanks for adding in your comments. I'm trying to view an 80Mhz signal that drives my HDL module. The signal is from a pll with an input clock of 80Mhz.Honored Contributor
