Altera_Forum
Honored Contributor
Honored Contributorusing SignalTap for internal RAM
Hello friends,
how can I use SignalTap to read the content of an internal RAM? ThanksForum Discussion
8 Replies
Altera_ForumYou can't. You can use SignalTap to monitor the signals connected to the RAM block and see what your system is doing but you can't access the RAM contents yourself with SignalTap.
You may be interested in another tool in Quartus called the In-System Memory Content Editor. It can let you access a RAM block if you set the correct option before compiling the project. You can only use it on single port RAMs though (as the editor will use the second port to access the RAM).- Altera_Forum
Thanks
As I've understood, for enabling "In-System Memory Content Editor" we have to use MegaWizard? Is that right? I didn't use MegaWizard for creating RAM. Is there anyway to enable the "In-System Memory Content Editor" in this case? - Altera_Forum
How did you implement your memory? If it is from SOPC builder / QSys you also have this option in the "memory initialization" section.
If you implemented it yourself with HDL it will be a lot harder to enable. - Altera_Forum
I implemented it myself with VHDL like this:
----------------------------------------------------- ----------------------------------------------------- library IEEE; use ieee.std_logic_1164.all; entity RAM is port( clock: in std_logic; data: in std_logic_vector (7 downto 0); write_address: in integer range 0 to 2047; read_address: IN integer range 0 to 2047; we: in std_logic; q: out std_logic_vector (7 downto 0) ); end RAM; architecture rtl of RAM is type mem is array(0 to 2047) of std_logic_vector(7 downto 0); signal ram_block : mem; begin process (clock) begin if (clock'event and clock = '1') then if (we = '1') then ram_block(write_address) <= data; end if; q <= ram_block(read_address); end if; end process; end rtl; ----------------------------------------------- ----------------------------------------------- As you see, this is a dual port RAM. Is it possible to use In-System Memory Content Editor for this dual-port RAM? Thanks in advance - Altera_Forum
No I this case it isn't possible. The only thing you can do is use SignalTap to monitor read_address, write:address, data, q and we to see what your system is doing, but as both ports are already used you can't add another module that could access the memory's contents for you while the system is running.
- Altera_Forum
But it's a "simple dual-port RAM". It's not a"true dual-port RAM".
I thought it's possible ... - Altera_Forum
Just think about how it would need to be implemented in hardware. When you ask Quartus to be able to access the memory from the Memory Content Editor, what it does is add extra logic to the FPGA image that is connected to the JTAG port one one side and to one of the memory block's ports on the other side, letting you access the memory contents through JTAG. If you are already using two ports (either simple or true), it would need a third port to allow access to the editor, and the FPGA's memory blocks don't have that possibility.
- Altera_Forum--- Quote Start --- But it's a "simple dual-port RAM". It's not a"true dual-port RAM". --- Quote End --- Simple dual-port is also dual-port. It uses both address/data ports of the RAM block, so there's none left for the ISMCE. Of course, if one port is read only and you don't need write access through ISMCE, it would be still possible by doubling the RAM. I didn't yet come across a Quartus option to use ISMCE this way, but it should work manually.
