using SignalTap for internal RAM

I implemented it myself with VHDL like this:

-----------------------------------------------------

-----------------------------------------------------

library IEEE;

use ieee.std_logic_1164.all;

entity RAM is

port(

clock: in std_logic;

data: in std_logic_vector (7 downto 0);

write_address: in integer range 0 to 2047;

read_address: IN integer range 0 to 2047;

we: in std_logic;

q: out std_logic_vector (7 downto 0)

);

end RAM;

architecture rtl of RAM is

type mem is array(0 to 2047) of std_logic_vector(7 downto 0);

signal ram_block : mem;

begin

process (clock)

begin

if (clock'event and clock = '1') then

if (we = '1') then

ram_block(write_address) <= data;

end if;

q <= ram_block(read_address);

end if;

end process;

end rtl;

-----------------------------------------------

-----------------------------------------------

As you see, this is a dual port RAM. Is it possible to use In-System Memory Content Editor for this dual-port RAM?

Thanks in advance