using SignalTap for internal RAM

Just think about how it would need to be implemented in hardware. When you ask Quartus to be able to access the memory from the Memory Content Editor, what it does is add extra logic to the FPGA image that is connected to the JTAG port one one side and to one of the memory block's ports on the other side, letting you access the memory contents through JTAG. If you are already using two ports (either simple or true), it would need a third port to allow access to the editor, and the FPGA's memory blocks don't have that possibility.