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Altera_Forum's avatar
Altera_Forum
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17 years ago

Using package in VHDL

Hi,

I am wondering if anybody could give me any hints how get this work. I write a function in a package and try to use it. The function is 7 segment decoder which gets in decimal number.

---------------------------------------------------------------------

PACKAGE SevenSegmentDecoding IS

Type SevenSegment is array (7 downto 1) of bit;

signal Seven_Segment : SevenSegment;

FUNCTION Integer2SevenSegment (i: IN INTEGER RANGE 0 to 15) RETURN

SevenSegment;

END PACKAGE SevenSegmentDecoding;

PACKAGE BODY SevenSegmentDecoding IS

FUNCTION Integer2SevenSegment (i: IN INTEGER RANGE 0 to 15) RETURN

SevenSegment is

begin

CASE i IS

WHEN 0 => Seven_Segment <= "0000001";

WHEN 1 => Seven_Segment <= "1001111";

WHEN 2 => Seven_Segment <= "0010010";

WHEN 3 => Seven_Segment <= "0000110";

WHEN 4 => Seven_Segment <= "1001100";

WHEN 5 => Seven_Segment <= "0100100";

WHEN 6 => Seven_Segment <= "0100000";

WHEN 7 => Seven_Segment <= "0001111";

WHEN 8 => Seven_Segment <= "0000000";

WHEN 9 => Seven_Segment <= "0001100";

WHEN 10=> Seven_Segment <= "1100000";

WHEN 11=> Seven_Segment <= "0110001";

WHEN 12=> Seven_Segment <= "1000010";

WHEN 13=> Seven_Segment <= "0110000";

WHEN 14=> Seven_Segment <= "0110000";

WHEN 15=> Seven_Segment <= "0111000";

END CASE;

END Integer2SevenSegment;

END SevenSegmentDecoding;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

use work.SevenSegmentDecoding.all;

ENTITY sjuseg IS

PORT ( input : IN INTEGER RANGE 0 to 15;

output : OUT SevenSegment

);

END sjuseg;

ARCHITECTURE behave OF sjuseg IS

BEGIN

input<=4;

output<=Integer2SevenSegment(input);

END behave;

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You are missing one line 

    LIBRARY work;
use work.SevenSegmentDecoding.all;
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Karl9, what exactly is the problem - i.e. what error message are you getting? Are the simulation results not what you expect?

    I don't think the "Library work;" line should make any difference - for any other library you would need this, but "work" is a special case and always visible. Of course that might be tool dependent since some tools don't fully implement the language properly, so you might need it after all.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    It did not help to add the line.

    Actually it complaints

    Quartus II:-

    Error (10808): VHDL error at sjuseg.vhd(16): unsupported reference to global signal or variable Seven_Segment

    ModelSim Altera:-

    ** Error: C:\WINDOWS\system32\sjuseg(16): Cannot access "seven_segment" from inside pure function "integer2sevensegment".

    ** Error: C:\WINDOWS\system32\sjuseg(16): Cannot drive signal 'seven_segment' from this subprogram.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The error isn't related to packages rather than incorrect FUNCTION syntax.

    Correct FUNCTION syntax is e.g. 

    WHEN 0 => RETURN "0000001";
WHEN 1 => RETURN "1001111";
---

    Also this statement isn't allowed

    input<=4;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi FvM and batfink,

    Thanks for your suggestions! I am new to VHDL so I did not know that this was wrong.

    Have a nice weekend to both of you.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Glad to hear you got it working. One other tip for you: some programmers think it's good practice to only have one return within a function (not specifically VHDL - actually it was a C programmer that introduced me to the idea). So you use a temporary variable in your function and return this at the end (I've shown you this below).

    This will make no difference to the operation of the function but as I said some people just consider it good practice to only have one return point to make the code more readable. Personally I think it depends on the particular code in question. 

    FUNCTION Integer2SevenSegment (i: IN INTEGER RANGE 0 to 15) RETURN 
SevenSegment is
    temp : SevenSgement;
begin
    CASE i IS
        WHEN 0 => temp := "0000001";
        WHEN 1 => temp := "1001111";
         WHEN 2 => temp := "0010010";
         WHEN 3 => temp := "0000110";
         WHEN 4 => temp := "1001100";
         WHEN 5 => temp := "0100100";
         WHEN 6 => temp := "0100000";
         WHEN 7 => temp := "0001111";
         WHEN 8 => temp := "0000000";
         WHEN 9 => temp := "0001100";
         WHEN 10=> temp := "1100000";
         WHEN 11=> temp := "0110001";
         WHEN 12=> temp := "1000010";
         WHEN 13=> temp := "0110000";
         WHEN 14=> temp := "0110000";
         WHEN 15=> temp := "0111000";
    END CASE;
    return temp;
END Integer2SevenSegment;
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    You are missing one line 

    LIBRARY work;
use work.SevenSegmentDecoding.all;

    --- Quote End ---

    work is always an implied library, like std.

    But OP's problems:

    1. You cannot drive signals from within a function. you have to drive them inside a process from the return value of a function ie.

    my_seven_seg <= Integer2SevenSegment(7);

    2. Although its legal VHDL to declare signals in packages, Altera will NOT support synthesising them. They are intended mainly as a debugging (in simulation) tool. Keep signals inside architectures.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Global signals (i.e. signals declared in packages) have never been synthesisable by any of the tool vendors as far as I'm aware - and fairly sensible too. If you think about it in terms of hardware description, then a global signal is effectively a wire dropping out of the sky into the middle of your component.

    They can however be very useful in system modelling and writing intelligent testbenches which verify correct functionality for you. In which case you can mask the gloabl signal assigment off in your synthesisable code:

    -- translate synthesis_off

    global_signal <= some_value;

    -- translate synthesis_on