--- Quote Start ---
You are missing one line
LIBRARY work;
use work.SevenSegmentDecoding.all;
--- Quote End ---
work is always an implied library, like std.
But OP's problems:
1. You cannot drive signals from within a function. you have to drive them inside a process from the return value of a function ie.
my_seven_seg <= Integer2SevenSegment(7);
2. Although its legal VHDL to declare signals in packages, Altera will NOT support synthesising them. They are intended mainly as a debugging (in simulation) tool. Keep signals inside architectures.