Using package in VHDL

Global signals (i.e. signals declared in packages) have never been synthesisable by any of the tool vendors as far as I'm aware - and fairly sensible too. If you think about it in terms of hardware description, then a global signal is effectively a wire dropping out of the sky into the middle of your component.

They can however be very useful in system modelling and writing intelligent testbenches which verify correct functionality for you. In which case you can mask the gloabl signal assigment off in your synthesisable code:

-- translate synthesis_off

global_signal <= some_value;

-- translate synthesis_on