use verilog module in vhdl and the test bench

I am trying to instantiating a verilog module in a vhdl design. There is no error shown after compile it but i can't get the corresponding result in the modelsim.

module i2c (             CLOCK,
             I2C_SCLK,        //I2C CLOCK
             I2C_SDAT,        //I2C DATA
             I2C_DATA,        //DATA:
             GO,              //GO transfor
             ENDS,            //ENDS transfor 
             W_R,             //W_R
             ACK,             //ACK
             RESET,
             //TEST
             SD_COUNTER,
             SDO
               );

component i2c     port(
         CLOCK : in std_logic;
         I2C_SCLK : out std_logic;
         I2C_SDAT : inout std_logic;
         I2C_DATA : in std_logic_vector(23 downto 0);
         GO    : in std_logic;
         ENDS : out std_logic;
         W_R : in std_logic;
         ACK : out std_logic;
         RESET : in std_logic;
         -- TEST
         SD_COUNTER : out std_logic_vector (5 downto 0);
         SDO : out std_logic
    );
    end component;